SyGuS Techniques in the Core of an SMT Solver

A synthesis conjecture asks whether there exists a structure for which some property holds universally. Traditionally, such conjectures are very challenging for automated reasoners. Syntax-guided synthesis (or SyGuS) is a recently introduced paradigm [1] where a user may provide syntactic hints to guide an automated reasoner in its search for solutions to synthesis conjectures. A number of recent solvers based on this paradigm have been successfully used in applications, including correct-by-construction program snippets [33] and for implementation of distributed protocols [36]. Satisfiability Modulo Theories (SMT) solvers have historically been used as subroutines for automated synthesis tasks [18, 35, 4, 37]. More recently, we have advocated in Reynolds et al. [29] for SMT solvers to play a more active role in solving synthesis conjectures, including being used as stand-alone tools. In particular, we have recently instrumented the SMT solver CVC4 [6] with new capabilities which make it efficient for synthesis conjectures, and entered it in the past several editions of the syntax-guided synthesis competition [2, 3] where it placed first in a number of categories. This work has shown that SMT solvers can be powerful tools for handling synthesis conjectures using two orthogonal techniques: 1. Synthesis via Quantifier Instantiation The first leverages the support in SMT solvers for firstorder quantifier instantiation, which has been used successfully in a number of approaches for automated theorem proving [16, 24, 30]. Quantifier-instantiation techniques developed for SMT can be extended and used as a complete procedure for certain classes of synthesis conjectures.